Advanced and emerging IC processes (e.g., 28 nm, 22 nm, etc.) cannot reliably print arbitrary geometric patterns because of complex interactions between neighboring features during the patterning processes. This problem is well known, and attempts to solve it have included the use of restricted design rules, gridded and/or unidirectional layout styles, etc.
Known techniques, however, do not effectively address the challenges posed by the most advanced (e.g., 22 nm and below) IC processes. In these processes, the pattern interaction distance (the maximum distance over which one geometric feature can affect the other neighboring features) is so large relative to the size of the smallest printable features that use of source-mask optimization (SMO) becomes highly desirable. But SMO is very computationally burdensome and, as a result, can only be practically employed on layouts of about 100 μm×100 μm.
Moreover, for SMO to be effective, the optimized area should adequately represent the complete (or nearly complete) universe of neighborhood patterns that appear on the chip. But traditional layout techniques (RDR, gridded, etc.) cannot achieve this goal—at least without significant sacrifices in layout density.